One process step used in copper damascene processing for the fabrication of integrated circuits is the formation of a “seed-” or “strike-” layer, which is then used as a base layer onto which copper is electroplated (electrofill). The seed layer carries the electrical plating current from the edge region of the wafer substrate (where electrical contact is made) to all trench and via structures located across the wafer substrate surface. The seed film is typically a thin conductive copper layer. It is separated from an insulating silicon dioxide or other dielectric by a barrier layer. The use of thin seed layers (which may also act simultaneously as copper diffusion barrier layers) which are either alloys of copper or other metals, such as ruthenium or tantalum, has also been investigated. The seed layer deposition process desirably yields a layer which has good overall adhesion, good step coverage (more particularly, conformal/continuous amounts of metal deposited onto the side-walls of an embedded structure), and minimal closure or “necking” of the top of the embedded feature.
To effectively plate a large surface area, a plating tooling makes electrical contact to the conductive seed layer in the edge region of the wafer substrate. There is generally no direct contact made to the central region of the wafer substrate. Thus, for highly resistive seed layers, the potential at the edge of the seed layer is significantly greater than at the central region of the seed layer, which is referred to as the “terminal effect”. Without appropriate means of resistance and voltage compensation, this large edge-to-center voltage drop leads to a non-uniform plating thickness distribution, primarily characterized by thicker plating at the wafer substrate edge. This non-uniform plating thickness will be even more pronounced as the industry transitions from 300 mm wafers to 450 mm wafers.